1. Field of the Invention
Embodiments of the invention relate to digital electronic circuits. More particularly, embodiments of the invention relate to high speed flip-flops used in integrated circuits.
2. Discussion of Related Art
A conventional flip-flop circuit includes a master latch and a slave latch. Data is supplied to each latch through transmission gates controlled by clock signals. Flip-flop circuits are typically used in microprocessors to provide maximum available logic clocking speeds. This is done by shortening the data-to-output times (or setup times) and clock-to-output times. FIG. 1 is a diagram showing a typical delay path in a digital circuit used in, for example, a microprocessor. The delay path includes first register 10, second register 12, and combination logic block 11. First and second registers 10 and 12 operate in sync with clock signal CLK and for the purposes of explanation, operate in sync with rising edges of clock signal CLK.
FIG. 2 is a timing diagram where first register 10 transfers data to combination logic block 11 at a first rising edge of clock signal CLK. Generally, there is a delay time T1 that is also called a “clock-to-output delay time” before data is output from first register 10. The clock-to-output delay time T1 is the time from a transition of clock signal CLK to the time when data is output from first register 10. Data output from first register 10 is transferred through combination logic block 11 and input to input terminal D2 of second register 12 before the rising edge of clock signal CLK. The time defined between a rising edge of clock signal CLK and an input of data signal T3 is referred to as the “data-to-output delay time” (or setup time). The data-to-output delay time T3 is the minimum time for maintaining a data signal input to second register 12 before a rising edge of clock signal CLK.
The data-to-clock time is the sum of the clock-to-output delay time T1 and the data-to-output delay time T3. In order to maximize the performance of the delay path, the data-to-clock time is minimized which assures maximum propagation time T2 for which data is transferred through combination logic block 11. Shortening the data-to-output delay time T3 may enhance the frequency of clock signal CLK, thereby improving circuit performance. By providing a longer delay path to combination logic block 11, the number of pipeline stages required by a microprocessor may be reduced. In addition, a sense-amplifier based flip-flop used for sensing a small signal is operable in higher speeds as compared to a conventional flip-flop. However, a sense amplifier flip-flop is limited by shortening the data-to-output delay time.